With the advent of microcontrollers had a problem 3.3V with the I2C bus, this was that, unlike other communication protocols such as SPI, I2C bus lines are bi-directional which means that if the device has not fed 3.3V 5V tolerant inputs was difficult to unify microcontroller and I2C peripherals with different levels of tension.

For those who understand the language Saxon can view the article in language original since what follows is only a summarized translation and free application note AN97055 Philips Semiconductors called and the occasional snack of mine.

I2C BUS LOGIC LEVELS

I2C specifies two types of logic levels:

a - From fixed levels.
B - dependent levels of the supply voltage. FIXED LEVELS

Oriented CMOS devices are not voltage levels higher than 5V. The levels of I / O specified are: State

input LOW [VII]: minimum 1.5V-0.5V max. HIGH-state input
[HIV]: minimum maximum VDDmax 3V + 0.5V.

LOW output state [VOL]: minimum maximum 0V 0.4V. HIGH-state output
[VOH]: open collector output, determined by VDD via pull-up resistor.

DEPENDENT LEVELS OF SUPPLY VOLTAGE

Oriented CMOS devices with voltage levels of 5V or less. The levels of I / O specified are: State

input LOW [VII]: minimum-maximum 0.5V 0.3VDD. HIGH-state input
[HIV]: minimum 0.7VDD VDDmax + 0.5V max.

LOW output state [VOL]: minimum 0V 0.4V maximum. HIGH-state output
[VOH]: open collector output, determined by VDD via pull-up resistor.

bus logic levels depend upon the pull-up resistors connected to VDD, leakage currents and, if any, resistance in series with the I / O of dipositvos connected to it. These values \u200b\u200bshould be selected so that duralte LOW state of the bus is present at least equal to 0.1VDD noise and the state of 0.2VDD HIGH.

LEVELS WAY ADAPTER

Next we see the proposed scheme to adapt two sections of a bus with different voltage levels:

The left section has pull-up resistors and devices that are connected to 3.3V, while the right section is devoted to 5V devices. The adapter is identical for both bus lines and consists of a pair of MOS-FET N-channel, the doors are connected to the lower of the voltages (3.3V), the sources section of "low voltage bus and drains to the section of "high voltage." HOW

  • Case 1: No device is the bus down the section of "low voltage" so this will be in HIGH state because of the pull-up resistors RP1 and RP2, the gate and source of the MOS-FET will be found to 3.3V so its Vgs is below the threshold and the MOS-FET not lead. This will allow the bus lines of the section of "high voltage" state remain high due to pull-up resistors RP3 and RP4 and so both sections will be in HIGH state but at different voltage levels.
  • Case2: A 3.3V device takes the bus to a low state then the source of MOS-FET is low while the door remains to 3.3V, the Vgs increases above the trigger threshold by the MOS-FET drive, thus the bus section of "high voltage" is due to the state LOW LOW 3.3V section and due to conduction of MOS-FET.
  • CaSO3: A 5V device takes the bus to a LOW state, the section of "low voltage" in the first instance via the lower drain-substrate diode of the MOS-FET internal to the Vgs exceeds the threshold value and drive MOS-FET which bus line of the section of "low voltage" will be a LOW via conduction of MOS-FET.

The 3 cases listed show that the logic levels are transferred in both directions of the bus, in case 2 and 3 are performing a function "wired AND" between the two bus lines as required by I2C specification.

You can use other voltage levels other than those listed if the left section of the circuit is the lower voltage, the maximum voltage is not critical as long as the MOS-FET can handle it but it should be noted that higher voltage the slower the fall of tension or "falling edge" because it takes longer to download the bus. The lowest voltage that can be used is given by the threshold voltage of MOS-FET or Vgs (th).

An additional feature of this circuit is the isolation of the section is low voltage of 3.3V when the voltage is switched off, in this case the voltage will be 0V and the MOS-FET will be disconnected because the Vgs remain below the threshold voltage, the section of "high voltage" is not affected and remain operational.

CIRCUIT MODIFICATION

If necessary also to isolate the section of "high voltage" when the voltage is turned off, then you should use the following circuit:

In this case if the voltage of 5V is tripped the section is isolated from the rest of the bus due to the transistors Q3 and Q4, the section of "low voltage" will also be isolated in case of disconnect as in the 3.3V previous case but now independent of 5V.

Since this circuit is symmetrical sections of "high voltage" and "low voltage" can be chosen arbitrarily in both the left and right of the circuit.

CONSIDERATIONS TO CONSIDER FOR MOS-FET

  • Type: Canal N
  • threshold gate [Vgs (th),] : Minimum 0.1V, 2V max. Resistance
  • driving [RDS (on)] : maximum 100Ω @ ID = 3mA, VGS = 2.5V.
  • input capacity [Ciss] : maximum 100pF @ VDS = 1V, VGS = 0V.
  • switching times [ton toff] : 50 ns max.
  • drain current [ID] : 10mA or higher.
Download: PDF