was like writing a bit and I decided this article is nothing new, it's actually quite obsolete but wanted to make a little history of how they started, in the era of semiconductors, the famous functions now use daily in the microprocessor without even realizing .... but with a small personal touches ... made with transistors and tested.
Without further ado, let the paper: PAR FUNCTION
is that function whose output (Y) there is the same value as its input (A).
The truth table and symbol are as follows:
and that your circuit (Click image to enlarge)
going from right to left we have what I call the stage output formed by R6, Q3, T3, D2 and Q4, whose mission is to provide a voltage high or low output (D3 and R7).
Suppose that the output this to a low level, then the collector of Q4 will have a voltage close to 0V, for that to happen in Q4 should be saturated condition whereas if the output was in a high state Q3 should be in saturation by the current flowing through R6 and D2 respectively, of what follows that R6, Q3 and D2 are the output stage for high and low for Q4.
A point to note is that Q3 and Q4 can not be activated simultaneously and that in this way would be an output short circuit, which is why it makes so-called phase excitation formed by R4, R5 and Q2 so that this does not happen.
look at the circuit, if there is no base current in Q2 this will be in court presenting a high impedance between the collector and emitter and causing current to flow through R4 to the base of Q3 by putting it in a state of saturation and, because that Q2 is not conducting, the voltage drop across the resistor R5 is 0V Q4 leaving the court, on the contrary if there is current at the base of Q2 this saturation states would plummet at the base voltage of Q3 that would cut and likewise increasing the voltage drop across R5 making Q4 is saturated. Finally would
to see the input stage and adaptation composed of Q1, D1, R1 and R2, as you can see the performance with respect to Q2 is more than just the issue here is in the entrance as if there were D1 and R3 any voltage above that level would be taken as 0.25 V high level of Q1. Now, the voltage applied to the input through R1 and D1 to be reflected in the BE junction of Q1 producing voltage drops in each of the most important elements here that produced in D1. As no current will circulate until the input level exceeds 0.9 V Q1 remains in state court and Q2 in saturation, the voltage exceeded the process is reversed only when Q1 reaches approximately 1.2 V (0.9 V + 0.25V).
So here I find it interesting? ... Then see the INVESTMENT FUNCTION
First
its symbol and truth table
and its corresponding circuit
As we can see both the stage output (R4, Q3, D2, Q4) as the excitation (R2, Q2, R3) are equal to the previous example so we will focus only on the input stage and adaptation consists of D1, Q1 and R1.
At first glance we notice that the provision in Q1 changed, the signal input is now through of the issuer, in this way R1 will flow through a stream that will be the sum of the current circulating through the BE junction of Q1 plus the circulation by the BC junction of that transistor and which circulates in turn by the union BE Q2.
In the presence of a low logic signal BE junction of Q1 will be directly polarized by the current flow put it in a state of saturation, as the CE voltage of Q1 will be very small in this state, Q2 will be cut . If instead the input signal has a logic high current flows through the BC junction of Q1 Q2 making into a state of saturation.
The diode D1 is placed to protect the entrance of Q1 to a possible negative value of voltage, if necessary would only input the voltage of the diode D1.
FUNCTION OR
Symbol and truth table
Circuit
Again no change in the output stages and excitement but as this function has two inputs (A and B) corresponding stage doubles, one input (A) is formed by R1, D1, Q1 and R3 and the other (B) R2, D2, Q2 R4 and R5 being common to both inputs.
If the entry at this level high current flows through R1, D1, the BE junction of Q1 and Q3 R3 is making the cut, the same will happen if the input B is high with the obvious difference that this time current will flow through R2, D2, BE union Q2 and R5.
If both inputs are high at Q1 and Q2 go into saturation simultaneously maintaining the status of Q3 cut in the opposite case (both inputs to low) Q1 and Q2 come into court for not running in the union movement BE of both which will saturate the collector voltage of Q3.
short we can say that
When A and B = 0 Q1 is off, Q2 is off, Q3 in saturation and output = 0
When A = 0 and B = 1 is in court Q1, Q2 in saturation, Q3 in court and out = 1
When A = 1 and B = 0 Q1 is in saturation cut Q2, Q3 in court and out = 1
When A and B = 1 is in saturation Q1, Q2 is in saturation, Q3 in court and out = 1 AND FUNCTION
Symbol and truth table
Circuit
As in previous cases the output stage is no different, if you do the stage of excitement which is double (Q6 and Q3). So that there exit a high level as Q3 Q6 both should be cut, if any of them goes into the output saturation level will lower, or that this is where the AND function occurs. On
entries both behave the same way as explained in the OR and equality with the difference that the collector outputs will be independent of excitation stage (Q1-Q6 and Q2-Q3) so I think no major problems in understanding the operation. Just say that input A will be composed of R1, D1, Q1, R3 and R4 and input B for R2, D2, Q2, R5 and R6.
short:
If A = 0 and B = 0 Q1, Q2, D1, D2 and Q4 does not lead; Q6, Q3 and Q5 are in saturation and output = 0
If A = 0 and B = 1 D1, Q1, Q3 and Q4 do not lead, D2, Q2, Q6 and Q5 if they lead and the output = 0
If A = 1 and B = 0 D2, Q2, Q6 and Q4 do not lead, D1, Q1, Q3 and Q5 if they lead and the output = 0
If A = 1 and B = 1 Q6, Q3 and Q5 do not lead, D1, D2, Q1, Q2, and Q4 if they lead and the output = 1
FUNCTION NOR symbol and truth table
Circuit
Here output and excitation are the same as those shown in the previous circuit stages input is equal to that explained in the circuit INVESTMENT function with the difference that here twice, the input A is composed of Q1, D1 and R1 and input B for Q2, D2 and R2.
Summary:
If A = 0 and B = 0
BE Q1 in conduction, BC
BE Q1 Q2 cut in driving, cutting BC
Q2 Q3, Q4 and Q6 in court; Q5 driving out
= 1
If A = 0 and B = 1
BE Q1 in conduction, in court
BC BE Q1 Q2 just driving, driving
BC Q2 Q3 and Q5 in court, Q4 and Q6 in conduction
Output = 0
If A = 1 and B = 0
just BE Q1 driving, driving
BC BE Q1 Q2 in driving, cutting BC
Q2 Q4 and Q5 in court, Q3 and Q6 in conduction
Output = 0
If A = 1 and B = 1
BE Q1 just leads, BC BE Q1 Q2
driving just leads, BC
driving Q2 Q3, Q4 and Q6 in conduction; Q5
cut output = 0
NAND FUNCTION symbol and truth table
Circuit
The circuit at this point the article should not present major problems of interpretation, the output stage is already known, the stage of excitement is the same as used in the OR functions, investors and PAR and the input stage and the role INVERSORA NOR and only differs from the previous one that the collectors of both inputs are linked to a single point, the base of Q3 because the stage of excitement is simple and twofold.
short:
If A = 0 and B = 0
BE Q2 driving
BC BE Q2 Q1 cut in driving, cutting BC
Q1 Q3 and Q5 in court; Q4 and D3 in driving out
= 1
If A = 0 and B = 1
BE Q2 in conduction, BC cut Q2 Q1 BE
just driving, driving
BC Q1 Q3 and Q5 in court, driving Q4 and D3 Output = 1
If A = 1 and B = 0
BE Q2 just driving, driving
BC BE Q2 Q1 in driving, cutting BC
Q1 Q3 and Q5 in court; Q4 and D3 in driving out
= 1
If A = 1 and B = 1
BE Q2 just driving, driving
BC BE Q2 Q1 just driving, driving
BC Q1 Q3 and Q5 in driving, Q4 and D3
cut output = 0
EXCLUSIVE OR FUNCTION
symbol and truth table
Circuit
Once again the output stages and arousal correspond to those already seen, as she had doubled the input stage to support A and B in which the components are distributed as follows: for entry to correspond D1, Q2 and R2 and input B D2, Q1 and R1 R3 part being common to both.
If you look closely at the circuit we see that the BE junction of Q1 and Q2 are connected through a limiting resistor (R1 and R2) respectively, if we continue to see appreciate that input A comes through resistance R2 to the base of Q2 and in turn the emitter of Q1, similarly input B leads to the base of Q1 and Q2 emitter. This connection keeps cutting state Q1 and Q2 provided the levels of A and B are equal, if these prices go into driving the affected transistor going into saturation and would make the cut to Q3.
short:
If A = 0 and B = 0
BE Q2 in court, in court
BE Q2 Q1 in court, in court
Q1 Q3 and Q4 Q5 in saturation and D3
cut output = 0
If A = 0 and B = 1
BE cut Q2, Q2 in court on driving
BE Q1, Q1 to Q3 and Q5
driving in Q4 and D3
cut in output = 1
driving
If A = 1 and B = 0
BE Q2 in driving, driving Q2 Q1 BE
in court Q1 Q3 and Q5
cut in Q4 and D3
cut in output = 1
driving
If A = 1 and B = 1
BE cut Q2, Q2 Q1 BE
in court in court in court
Q1 Q3 and Q4 Q5 in saturation and D3
cut output = 0
hope you like this mini explanation of discrete gates, I want to clarify that this explanation is only to clarify concepts and should not be used to replace these functions in a circuit because for that they were reliable it must meet certain conditions of mating in the transistors that would be very difficult to obtain in practice, besides being wasteful.
577 KB Author: Web
Gariel origin: www.geglab.com.ar
0 comments:
Post a Comment